# The Three Dimensional Surface on A Two Dimensional Plane Question

Homework-111.What are response contours? Illustrate for a k-factor problem with k=2,3. (5075 words)
2. A response that is a smooth function over the levels of two factors may or
may not be similar when viewed over different levels of a third factor. Can you
explain this statement? Provide example.
3.Suppose a second-order model in three factors had been fitted. Using
canonical analysis, how could you detect and analyze a sloping ridge system?
Describe and illustrate two different kinds of limiting models for a sloping ridge
and their corresponding canonical form?
4.
1. In the MMC of Figure 1,
1.1) If the dc-side voltage is 500 kV, using IGBTs with a voltage rating of 6.5 kV, explain the way you
size the number of submodules N in each arm and write it down with enough supporting
justification. Determine the number of submodules.
1.2) Repeat part 1.2) if the submodules are replaced with full-bridge submodules.
1.3) Write the mathematical equations to prove that if a sine-triangular PWM with 3rd order
harmonic injection employed, 4th order harmonic will appear in the circulating current.
Figure 1: The circuit diagram of the MMC.
2- The components specify for a resonant buck converter, as shown in the following figure are:
𝐿𝑟 = 4𝜇𝐻, 𝐶𝑟 = 47𝑛𝐹 and 𝐿 = 1𝑚𝐻, and 𝐶 = 150𝜇𝐹. The input voltage is 48V and output voltage is
12V. The load resistance is 2Ω. Answer the following questions when the converter is operating in
2.1) Find the switching frequency
2.2) Find the duration of resonant mode
2.3) Find the peak voltage across the resonant capacitor.
2.4) Determine the minimum duty cycle of the gate signal, in which the ZVS is guaranteed.
2.5) Determine the rating values (current and voltage) of the power MOSFET.
2.6) Assuming a rise time and fall time of 𝑡𝑓 = 𝑡𝑟 = 100 𝑛𝑠, calculate the MOSFET turn-on and turnoff
losses.
2.7) What happens if the load varies in the range of 1Ω to 10 Ω.
3. In the power circuit of the following figure, IGBTs can be turned off either with a zero voltage applied
to the gate-emitter (unipolar turn off) or with a negative voltage (bipolar turn-off). In high-power
applications, the bipolar turn off is the common practice. Using the parasitic inductances 𝐿𝜎1 and 𝐿𝜎2
shown in the figure, explain the risk of using unipolar turn off and justify the reason behind using the
bipolar turn off.
ECE6331-A: Power
Electronic Circuits
Losses in Hard Switching Converters
2
2
Soft Switching
Semiconductor devices are switched on or off at the zero
crossing of their voltage or current waveforms:
•Zero-current switching (ZCS): Switching transition occurs
at zero current.
•Zero-voltage switching (ZVS): Switching transition occurs
at zero voltage.
3
3
ZVS and ZCS
Illustration of ZVS and ZCS for a power switch: (a) ZVS turn-on and turn-off
transitions; (b) ZCS turn-on and turn-off transitions.
4
4
Trajectories of current and voltage
5
5
Undamped Series-Resonant Circuit
6
6
7
7
Resonant Switches
Configurations of the zero-current switch
Configurations of the zero-voltage switch
8
8
Quasi-resonant Converters
In a conventional PWM converter, replace
the PWM switch network with a switch
network containing resonant elements.
9
9
Quasi-Resonant Switch Cells
10
10
The ZCS Quasi-Resonant Switch Cell
11
11
Waveforms of the Half-wave ZCS QuasiResonant Switch Cell
Waveforms:
Waveforms:
Each switching period contains four
subintervals
12
12
Subinterval 1

13
13
Subinterval 2

14
14
Subinterval 2
15
15
Boundary of ZCS

16
16
Subinterval 3
• All semiconductor devices are off and the equivalent
circuit is:
17
17
Subinterval 4

18
18
Maximum Switching Frequency

19
The length of the fourth subinterval cannot be negative, and the switching period
must be at least long enough for the tank current and voltage to return to zero by
the end of the switching period. The angular length of the switching period is
19
The Average Output Voltage
The average switch input current is given by:
20
20
The Average Output Voltage (Con’ed)
• During subinterval 2, we have:
21
21
The Average Output Voltage (Con’ed)
• First term: integral of the capacitor current over
subinterval 2. This can be related to the change in
capacitor voltage:
Substitute results for the two integrals:
Substitute into expression for average
switch input current:
22
22

23
23
The Average Output Voltage (Con’ed)
This is of the form:
24
24
ZCS Boundary
ZCS boundary
1
0.9
0.8
0.8
0.7
0.6
0.6
Js
0.5
0.4
0.4
0.3
0.2
0.2
F = 0.1
0
0
0.2
0.4
0.6
0.8
1

25
25
Properties of ZCS Resonant DC-DC
Converter
• Peak current of switch
– High when compared to the output current
– Conduction losses are higher than the hardswitching
26
26
ZCS Switch Cell
27
27
Analysis of Full-Wave ZCS
• Analysis in the full-wave case is nearly the same as in the half-wave
case. The second subinterval ends at the second zero crossing of the
tank inductor current waveform. The following quantities differ:
28
28
Analysis of Full-Wave ZCS
29
29
Resonant Switches for ZVS
Configurations of the zero-voltage switch
30
30
The ZVS Quasi-resonant Switch Cell
• A half-wave version based on the PWM buck
converter
31
31
Half-Wave ZVS Resonant-Switch
Converter
32
32
Full-wave ZVS
When switch T is implemented by a MOSFET and an anti-parallel diode, D, as shown
in Fig. (b), the voltage across capacitor Cr is clamped by D to positive values, and the
resonant switch is operating in a half-wave mode.
On the other hand, when switch T is implemented by a MOSFET in series with D, as
shown in Fig. (C), and the voltage across Cr can oscillate freely, then the resonant
switch is operating in a full-wave mode.
Notice that in a current-mode resonant switch, the resonant interaction between Lr
and Cr occurs during the major portion of the on-time; while in a
voltage-mode resonant switch, the resonant interaction occurs during the major
portion of the off-time.
33
33
Full-Wave ZVS Resonant-Switch
Converter
In the full-wave version, the voltage across Cr can
oscillate freely and become negative too as shown
below. ZVS can be implemented in the second zero
voltage crossing point of VCr.
34
34
ZVS Resonant-Switch Converter
35
35
Comparison of ZCS and ZVS

36
36
Resonant Pole Converter
37
37
Resonant Pole Converter
• Switch turn on and off with zero voltage
– Maximum voltage is clamped to input voltage
• Lf is small when compared to hard switching
– Its current is both positive and negative
• T+ conduct current and it is turned off
– Voltage over it is zero because of C+
38
38
Resonant Pole Converter
39
39
Operation (1/2)
40
40
Operation (2/2)
41
41
Control of output voltage
42
42
Modular Multilevel Converters
Half-Bridge and Full-Bridge Modules
2
✓ Provides scalability and
modularity
✓ More modules:
➢ More voltage levels
➢ Higher voltages
➢ More redundancy
3
✓ Provides scalability and
modularity
✓ More modules:
➢ More voltage levels
➢ Higher voltages
➢ More redundancy
4
𝑣 = 𝑉𝐷𝐶 + 𝑉෡𝑎 cos 𝜔𝑡
𝑖 = 𝐼𝐷𝐶 + 𝐼෡𝑎 cos 𝜔𝑡 − 𝜑
2𝑉𝐷𝐶 𝐼𝐷𝐶 + 𝑉෡𝑎 𝐼෡𝑎 cos𝜑 = 0
5
Assuming the same amount for the total capacitor voltages Vcap, the
operating region with cascaded full-bridge modules is wider.
6
The Modular Multilevel Converter (MMC)
The MMC is built based upon cascaded
half-bridge submodules (SMs).
7
Basics of Operation of the MMC
𝑉𝐷𝐶
𝑣
2𝑠
➢ On the AC side, sinusoidal
voltages are provided.
produce AC and DC
voltage components.

𝑉𝐷𝐶
2
𝑉𝐷𝐶
2
𝑉𝐷𝐶
2
0
𝑉𝐷𝐶
𝑉𝐷𝐶
2
𝑉𝐷𝐶
𝑉𝐷𝐶
2
𝑉𝐷𝐶
2
0
𝑉𝐷𝐶
2
8
9
𝑣𝑢𝑝
𝑉𝐷𝐶
=
− 𝑉෡𝑠 sin 𝜔𝑡
2
𝑣𝑠 = 𝑉෡𝑠 sin 𝜔𝑡
𝑣𝑙𝑜𝑤
𝑉𝐷𝐶
=
+ 𝑉෡𝑠 sin 𝜔𝑡
2
Power balance for three-phase converter:
𝑖𝑢𝑝 =
𝐼𝐷𝐶 1
+ 𝐼෡𝑠 sin 𝜔𝑡 − 𝜑
3
2
𝑖𝑠 = 𝐼෡𝑠 sin 𝜔𝑡 − 𝜑
𝑖𝑙𝑜𝑤 =
𝐼𝐷𝐶 1
− 𝐼෡𝑠 sin 𝜔𝑡 − 𝜑
3
2
3
𝑉෡ 𝐼෡ cos 𝜑 = 𝑉𝐷𝐶 𝐼𝐷𝐶
2 𝑠𝑠
SM Capacitor Voltage Balancing
Similar to any other
multilevel converter
topology, the MMC
needs an active
voltage balancing
strategy to balance and
maintain the SM
capacitor voltages at
VDC/N
11
SM Capacitor Voltage Balancing
12
SM Capacitor Voltage Balancing for a 5Level MMC
N=4
13
Circulating Current
𝑖𝑢𝑝,𝑗 =
𝑖𝑗
2
+
𝑖𝐷𝐶
3
𝑖𝑗
𝑖𝑙𝑜𝑤,𝑗 = − +
2
+𝑖𝑧,𝑗
𝑖𝐷𝐶
3
𝑖𝑧,𝑗 =
+𝑖𝑧,𝑗
14
𝑖𝑢𝑝,𝑗 + 𝑖𝑙𝑜𝑤,𝑗 𝑖𝐷𝐶

2
3
Circulating Currents

Circulating currents contain negative sequence components with the
frequencies twice the fundamental one (predominantly a 2nd–order
harmonic component)

If not properly controlled/suppressed, they:

increase the arm rms and peak currents, which consequently increase the converter
power losses, rating values of the semiconductor devices and the ripple magnitude
of the SM capacitor voltages.
Increasing the arm inductor would reduce the magnitude of
circulating currents. However, this would adversely impact the
magnitude of the maximum attainable voltage on the AC-side of the
converter
Dynamics of Circulating Currents
𝑖𝑢𝑝,𝑗 + 𝑖𝑙𝑜𝑤,𝑗 𝑖𝐷𝐶
𝑖𝑧,𝑗 =

2
3
𝑑𝑖𝑢𝑝,𝑗
𝑉𝐷𝐶
− 𝑣𝑢𝑝,𝑗 = 𝐿𝑜
+ 𝑅𝑜 𝑖𝑢𝑝,𝑗 + 𝑣𝑗
2
𝑑𝑡
𝑑𝑖𝑙𝑜𝑤,𝑗
𝑉𝐷𝐶
− 𝑣𝑙𝑜𝑤,𝑗 = 𝐿𝑜
+ 𝑅𝑜 𝑖𝑙𝑜𝑤,𝑗 + 𝑣𝑗
2
𝑑𝑡

Circulating current dynamics:
𝐿𝑜
Lo
𝑑𝑖𝑧,𝑗
𝑉𝐷𝐶 𝑣𝑢𝑝,𝑗 + 𝑣𝑙𝑜𝑤,𝑗
𝑖𝐷𝐶
+ 𝑅𝑜 𝑖𝑧,𝑗 =

− 𝑅𝑜
𝑑𝑡
2
2
3
diz , j
dt
+ Roiz , j = vz , j
Circulating Current Control: PR
Controller

Circulating Current Dynamics:
𝐿𝑜
Lo

𝑑𝑖𝑧,𝑗
𝑉𝐷𝐶 𝑣𝑢𝑝,𝑗 + 𝑣𝑙𝑜𝑤,𝑗
𝑖𝐷𝐶
+ 𝑅𝑜 𝑖𝑧,𝑗 =

− 𝑅𝑜
𝑑𝑡
2
2
3
diz , j
dt
+ Roiz , j = vz , j
PR Controller:
K p1 +
K i1s
K s
+ 2 i2 2
2
s + n1 s + n 2
2
Where ωn1 and ωn2 are tuned to 2nd and 4thorder harmonics.
Circulating Current Control: PI
Controllers
𝑖𝑧,𝑎 = 𝐼2𝑓 sin 2𝜔0 𝑡 + 𝜑0
2𝜋
+ 𝜑0
3
2𝜋
= 𝐼2𝑓 sin 2𝜔0 𝑡 + 𝜑0 +
3
𝑖𝑧,𝑏 = 𝐼2𝑓 sin 2 𝜔0 𝑡 −
2𝜋
+ 𝜑0
3
2𝜋
= 𝐼2𝑓 sin 2𝜔0 𝑡 + 𝜑0 −
3
𝑖𝑧,𝑐 = 𝐼2𝑓 sin 2 𝜔0 𝑡 +
𝐼2𝑓 is the peak value of the double line-frequency
circulating current.
𝜔0 is the fundamental frequency and 𝜑0 is its initial
phase angle.
Circulating Current Control: PI
Controllers
𝑇𝑎𝑏𝑐/𝑑𝑞 =
2
3
𝑐𝑜𝑠𝜃
−𝑠𝑖𝑛𝜃
where 𝜃 = −2𝜔0 𝑡
2𝜋
3
2𝜋
−𝑠𝑖𝑛 𝜃 −
3
𝑐𝑜𝑠 𝜃 −
2𝜋
3
2𝜋
−𝑠𝑖𝑛 𝜃 +
3
𝑐𝑜𝑠 𝜃 +
Circulating Current Control: PI
Controllers
By rewriting
Lo
diz , j
dt
+ Roiz , j = vz , j in abc form
𝑖
𝑖𝑧,𝑎
𝑣𝑧,𝑎
𝑑 𝑧,𝑎
𝑣𝑧,𝑏 = 𝐿0
𝑖𝑧,𝑏 + 𝑅0 𝑖𝑧,𝑏
𝑑𝑡
𝑣𝑧,𝑐
𝑖𝑧,𝑐
𝑖𝑧,𝑐
Substituting and multiplying the transformation matrix 𝑇𝑎𝑏𝑐/𝑑𝑞 yields
𝑢𝑧,𝑑
𝑑 𝑖2𝑓,𝑑
0
=
𝐿
+
0
𝑢𝑧,𝑞
2𝜔0 𝐿0
𝑑𝑡 𝑖2𝑓,𝑞
𝑖2𝑓,𝑑
𝑖2𝑓,𝑑
−2𝜔0 𝐿0

+ 𝑅0
𝑖2𝑓,𝑞
𝑖2𝑓,𝑞
0
Circulating Current Control: PI
Controllers
𝑖2𝑓,𝑑 = 1.5 𝐼2𝑓 sin 𝜑0
𝑖2𝑓,𝑞 = 1.5 𝐼2𝑓 cos 𝜑0
Pulse Width Modulation
22
Direct Modulation
𝑟𝑒𝑓
𝑛𝑢𝑝,𝑗
𝑉𝐷𝐶
𝑟𝑒𝑓
− 𝑣𝑗
=𝑁 2
𝑉𝐷𝐶
𝑟𝑒𝑓
𝑛𝑙𝑜𝑤,𝑗
𝑉𝐷𝐶
𝑟𝑒𝑓
+ 𝑣𝑗
=𝑁 2
𝑉𝐷𝐶
Indirect Modulation
𝑟𝑒𝑓
𝑛𝑢𝑝,𝑗
𝑉𝐷𝐶

𝑟𝑒𝑓
𝑧
− 𝑣𝑗 − 𝑣𝑟𝑒𝑔,𝑗 − 𝑣𝑟𝑒𝑔,𝑗
=𝑁 2
∑𝑁
𝑖=0 𝑣𝑐,𝑢𝑝,𝑖,𝑗
𝑟𝑒𝑓
𝑉𝐷𝐶

𝑟𝑒𝑓
𝑧
+ 𝑣𝑗 − 𝑣𝑟𝑒𝑔,𝑗 − 𝑣𝑟𝑒𝑔,𝑗
2
=𝑁
∑𝑁
𝑖=0 𝑣𝑐,𝑙𝑜𝑤,𝑖,𝑗
𝑛𝑙𝑜𝑤,𝑗
Control of a Grid-Connected MMC
25
Closed-Loop Control of the MMC
Closed-Loop Control of the MMC
HVDC Transmission System
P =
VDC. IDC
MMC-Based HVDC Transmission
Half-Bridge SM
Full-Bridge SM
The clamp-double SM
29
DC-Side Fault
Half-Bridge SM
Full-Bridge SM
The clamp-double SM
30
Alternative SM Circuit: Full-Bridge SM
Full-Bridge SM
Half-Bridge SM
31
Full-Bridge SM
Full-Bridge MMC During DC-Side Fault
Current path in a Full-Bridge SM during a DCside short circuit fault
32
Alternative SM Circuit: Clamp-Double SM
Clamp-Double
Half-Bridge
SM
33
SM
Clamp-Double MMC During DC-Side Fault
Half-Bridge
SM path
Current
in aFull-Bridge
Clamp-Double
SM
SM
during a DC-side short circuit fault
34

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